verilog-ext

Homepage: https://github.com/gmlarumbe/verilog-ext

Author: Gonzalo Larumbe

Updated: 2024-Dec-11

Summary

SystemVerilog Extensions

Commentary

Extensions for Verilog Mode:

 - Tree-sitter `verilog-ts-mode' support
 - Project management
 - Improved syntax highlighting for `verilog-mode'
 - Find definitions and references with builtin `xref' backend
 - Auto-completion with dot and scope completion
 - Hierarchy extraction and navigation
 - LSP configuration for `lsp-bridge', `lsp-mode', `eglot' and `lspce'
 - Support for many linters via `flycheck'
 - Beautify modules and instances
 - Code navigation functions for RTL and Verification environments
 - Templates insertion via `hydra': custom and `yasnippet' based
 - Code formatter via `apheleia'
 - Compilation-based utilities
 - Improve `imenu': detect instances, classes and methods
 - Add support for `which-func'
 - Code folding via `hideshow'
 - Project tags, typedef analysis and caching
 - `time-stamp' auto-configuration
 - Convert block end comments to names
 - Port connections utilities

Dependencies

• ag
• align
• apheleia
• async
• eglot
• flycheck
• hideshow
• hierarchy
• hydra
• imenu
• lsp-mode
• lsp-verilog
• make-mode
• map
• outline
• outshine
• ripgrep
• test-hdl
• test-hdl-setup-package
• test-hdl-setup-straight
• tree-widget
• verilog-mode
• verilog-ts-mode
• which-func
• xref
• yasnippet